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LLC2_API
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00001 /***************************************************************************** 00002 * 00003 * File: acq32ioctl.h - Application interface to acq32 Linux driver 00004 * 00005 * $RCSfile: acq32ioctl.h,v $ 00006 * 00007 * Copyright (C) 1999 D-TACQ Solutions Ltd 00008 * not to be used without owner's permission 00009 * 00010 * Description: 00011 * 00012 * $Id: acq32ioctl.h,v 1.38.4.2 2007/02/19 15:51:44 pgm Exp $ 00013 * $Log: acq32ioctl.h,v $ 00014 * Revision 1.38.4.2 2007/02/19 15:51:44 pgm 00015 * correct size typ on ioctl 00016 * 00017 * Revision 1.38.4.1 2006/01/28 18:18:55 pgm 00018 * ST_CAPDONE 00019 * 00020 * Revision 1.38 2002/11/06 14:39:20 pgm 00021 * *** empty log message *** 00022 * 00023 * Revision 1.37 2002/11/06 14:39:01 pgm 00024 * *** empty log message *** 00025 * 00026 * Revision 1.36 2002/08/09 14:13:20 pgm 00027 * *** empty log message *** 00028 * 00029 * Revision 1.35 2002/06/16 16:31:39 pgm 00030 * *** empty log message *** 00031 * 00032 * Revision 1.34 2002/07/29 08:07:33 pgm 00033 * *** empty log message *** 00034 * 00035 * Revision 1.33 2002/07/24 07:20:59 pgm 00036 * MAXCHUNKSIZE 00037 * 00038 * Revision 1.32 2002/07/19 18:40:04 pgm 00039 * add irq 00040 * 00041 * Revision 1.31 2002/05/31 08:32:50 pgm 00042 * rh7.3 compile works 00043 * 00044 * Revision 1.30 2002/02/27 03:09:48 pgm 00045 * add help part 1 00046 * 00047 * Revision 1.29 2002/02/27 02:09:06 pgm 00048 * getSyncRoute 00049 * 00050 * Revision 1.28 2002/02/14 16:26:23 pgm 00051 * DIx arg for setModeTriggeredContinuous 00052 * 00053 * Revision 1.27 2002/02/10 18:16:05 pgm 00054 * FAST_MULTI opt 00055 * 00056 * Revision 1.26 2002/02/02 14:44:42 pgm 00057 * waitEvent (not complete), multimaster updates 00058 * 00059 * Revision 1.25 2001/10/21 09:08:40 pgm 00060 * selectThresholdDetector etc 00061 * 00062 * Revision 1.24 2001/10/20 20:44:42 pgm 00063 * *** empty log message *** 00064 * 00065 * Revision 1.23 2001/10/14 09:07:15 pgm 00066 * *** empty log message *** 00067 * 00068 * Revision 1.22 2001/10/13 15:30:10 pgm 00069 * ACQ32_IOG_READ/WRITE funcs for ioctl target mem access 00070 * 00071 * Revision 1.21 2001/09/07 09:54:54 pgm 00072 * new keywords 00073 * 00074 * Revision 1.20 2001/08/19 20:24:24 pgm 00075 * threshold commands 00076 * 00077 * Revision 1.19 2001/08/18 20:06:41 pgm 00078 * resetGUT 00079 * 00080 * Revision 1.18 2001/06/26 18:51:19 pgm 00081 * getConfig etc 00082 * 00083 * Revision 1.17 2001/06/23 11:22:40 pgm 00084 * for release 00085 * 00086 * Revision 1.16 2001/06/04 19:28:38 pgm 00087 * *** empty log message *** 00088 * 00089 * Revision 1.15 2001/05/25 17:17:59 pgm 00090 * time for release now 00091 * 00092 * Revision 1.14 2001/05/03 18:52:11 pgm 00093 * docs DUMDMA 00094 * 00095 * Revision 1.13 2001/04/16 15:37:48 pgm 00096 * ready for release 00097 * 00098 * Revision 1.12 2001/03/30 20:17:01 pgm 00099 * UDMA first cut working 00100 * 00101 * Revision 1.11 2001/03/25 19:19:04 pgm 00102 * first cut i2o command processing 00103 * 00104 * Revision 1.10 2000/10/28 21:19:15 pgm 00105 * getSetNumSamples 00106 * 00107 * Revision 1.9 2000/10/08 19:57:01 pgm 00108 * TriggeredContinuous etc 00109 * 00110 * Revision 1.8 2000/10/01 21:53:51 pgm 00111 * bigdump, sping, debug etc 00112 * 00113 * Revision 1.7 2000/09/26 19:46:52 pgm 00114 * GATED_CONTINUOUS pre/post, lseek, spin 00115 * 00116 * Revision 1.6 2000/07/01 07:25:39 pgm 00117 * SOFT_CONTINUOUS 00118 * 00119 * Revision 1.5 2000/06/11 19:29:29 pgm 00120 * getChannelMask 00121 * 00122 * Revision 1.4 2000/06/04 18:41:00 pgm 00123 * Signal Conditioning protocol implemented 00124 * 00125 * Revision 1.3 2000/05/20 08:27:03 pgm 00126 * ICD REV6 function codes 00127 * 00128 * Revision 1.2 1999/11/20 21:20:30 pgm 00129 * 991120 time for bed 00130 * 00131 * Revision 1.1.1.1 1999/10/25 13:14:08 pgm 00132 * linux include 00133 * 00134 * Revision 1.7 1999/10/20 19:57:16 pgm 00135 * mixed in ebsa driver funcs + new rom offset hakker 00136 * 00137 * Revision 1.6 1999/10/14 22:51:50 pgm 00138 * simul engine runs - SHIP IT QUICKcvs status | grep Status 00139 * 00140 * Revision 1.5 1999/10/14 21:10:28 pgm 00141 * master command handling works 00142 * 00143 * Revision 1.4 1999/10/12 21:24:20 pgm 00144 * master command handling top down connection OK 00145 * 00146 * Revision 1.3 1999/10/12 10:23:47 pgm 00147 * basic master command/readback struct WORKS 00148 * 00149 * Revision 1.2 1999/10/02 21:27:14 pgm 00150 * first pass compile OK. /proc/acq32 stuffed 00151 * 00152 * Revision 1.1 1999/10/02 19:33:46 pgm 00153 * lets go 00154 * 00155 * 00156 \*****************************************************************************/ 00157 00158 #ifndef _ACQ32IOCTL_H_ 00159 #define _ACQ32IOCTL_H_ 00160 00161 #include <asm/ioctl.h> 00162 #include <asm/types.h> 00163 00164 /* 00165 * whence arg for seek 00166 */ 00167 00168 #define SEEK_TRIG (SEEK_END+1) 00169 00170 /* 00171 * Ioctl definitions 00172 */ 00173 00174 #define ACQ32_IOC_MAGIC 'a' 00175 00176 #define ACQ32_IOCRESET _IO(ACQ32_IOC_MAGIC, 0) 00177 00178 /* 00179 * S means "Set" through a ptr, 00180 * T means "Tell" directly with the argument value 00181 * G means "Get": reply by setting through a pointer 00182 * Q means "Query": response is on the return value 00183 * X means "eXchange": G and S atomically 00184 * H means "sHift": T and Q atomically 00185 */ 00186 00187 #define ACQ32_IOCGMEM _IOR(ACQ32_IOC_MAGIC, 1, void*) 00188 #define ACQ32_IOSLIMIT _IO (ACQ32_IOC_MAGIC, 2 ) // set readout limit 00189 00190 // arg for LIMIT is limit count of samples per read 00191 00192 #define ACQ32_IOSFORMAT _IO (ACQ32_IOC_MAGIC, 3 ) // set output format 00193 00194 #define ACQ32_IOARMSPIN _IO(ACQ32_IOC_MAGIC, 4 ) // make ARM spin 00195 #define ACQ32_IOARMRESET _IO(ACQ32_IOC_MAGIC, 5 ) // reset ARM 00196 00197 #define ACQ32_IOSDEBUG _IOW(ACQ32_IOC_MAGIC, 6, int) // set debug level 00198 // arg for format is 00199 00200 enum ChannelMode { 00201 CM_BINARY, 00202 CM_HEX, 00203 CM_DEC, 00204 CM_VOLTS, 00205 CM_BIGEND, 00206 00207 CM_EXCLUSIVE_OPTS = 0xf, 00208 00209 CM_LINENUMS = 0x40, 00210 CM_DOS_LINES = 0x80 00211 }; 00212 00213 /* 00214 * access the mailboxes 0 <= ix <= 3 00215 */ 00216 00217 #define ACQ32_IO_MBX_NR 10 00218 00219 #define ACQ32_IOSMBX( ix ) \ 00220 _IO (ACQ32_IOC_MAGIC, ACQ32_IO_MBX_NR+(ix) ) 00221 00222 #define ACQ32_IOGMBX( ix ) \ 00223 _IOR(ACQ32_IOC_MAGIC, ACQ32_IO_MBX_NR +(ix), unsigned*) 00224 00225 #define ACQ32_IOSROM_WORD_A01 _IO( ACQ32_IOC_MAGIC, 14 ) 00226 #define ACQ32_IOCHARDRESET _IO (ACQ32_IOC_MAGIC, 15 ) /* debugging tool */ 00227 #define ACQ32_IOSENDI2O _IO (ACQ32_IOC_MAGIC, 16 ) 00228 #define ACQ32_IOREAD_LOCALBUF _IO (ACQ32_IOC_MAGIC, 17 ) 00229 #define ACQ32_IOREAD_GETPHYSICAL _IO (ACQ32_IOC_MAGIC, 18 ) 00230 #define ACQ32_IOG_PCIREGS_OFFSET _IOR(ACQ32_IOC_MAGIC, 19, unsigned* ) 00231 00232 /* 00233 * acq32 memory read/write 00234 */ 00235 00236 struct ACQ32_RW_DEF { 00237 unsigned offset; 00238 union { 00239 __u16 w; 00240 __u32 l; 00241 } 00242 data; 00243 }; 00244 00245 #define ACQ32_IOG_READ32 _IO (ACQ32_IOC_MAGIC, 20 ) 00246 #define ACQ32_IOS_WRITE32 _IO (ACQ32_IOC_MAGIC, 21 ) 00247 #define ACQ32_IOG_READ16 _IO (ACQ32_IOC_MAGIC, 22 ) 00248 #define ACQ32_IOS_WRITE16 _IO (ACQ32_IOC_MAGIC, 23 ) 00249 00250 /* 00251 * waiting for events 00252 */ 00253 struct ACQ32_WAIT_DEF { 00254 unsigned event_mask; // currently only 1 event is valid: OnStop == 1 00255 unsigned timeout; // timeout in ticks 00256 }; 00257 00258 #define ACQ32_IOS_WAIT_EVENT _IO (ACQ32_IOC_MAGIC, 24 ) 00259 00260 /* 00261 * interrupt masking (for realtime performance) 00262 * parameter is 32 bit mask for irq 0..31 00263 */ 00264 00265 #define ACQ32_IOS_INTS_ENABLE _IOW(ACQ32_IOC_MAGIC, 25, unsigned ) 00266 #define ACQ32_IOS_INTS_DISABLE _IOW(ACQ32_IOC_MAGIC, 26, unsigned ) 00267 00268 /* 00269 * how much kmem is there ? - use this ioctl with arg == order mask 00270 * eg 0x10 = O5, 0x18 = O5+O4 00271 * allocates until out of memory, reports in klog, 00272 * blocks, and frees up on signal 00273 */ 00274 00275 #define ACQ32_IOS_SWALLOW_KMEM _IOW(ACQ32_IOC_MAGIC, 27, unsigned ) 00276 #define ACQ32_IOS_VALIDATE_BIGBUF _IOW(ACQ32_IOC_MAGIC, 28, unsigned ) 00277 00278 #define ACQ32_IOC_MAXNR 29 00279 00280 00281 /* 00282 * ioctls are less important that command strings: 00283 */ 00284 00285 /* 00286 * channel commands - apply to row dev (non-volatile) 00287 * or channel dev (volatile) 00288 */ 00289 00290 #define CC_FORMAT "format" 00291 #define CC_FORMAT_BIN "bin" 00292 #define CC_FORMAT_BIGEND "bigendian" 00293 #define CC_FORMAT_HEX "hex" 00294 #define CC_FORMAT_DEC "dec" 00295 #define CC_FORMAT_VOLTS "volts" 00296 #define CC_FORMAT_LINENUMS "lines" 00297 #define CC_FORMAT_DOS "dos" 00298 00299 #define CC_LIMIT "limit" // limit n - limit output to n samples 00300 00301 #define CC_SEEK "seek" // seek {whence} n 00302 #define CC_SEEK_BEGIN "start" 00303 #define CC_SEEK_END "end" 00304 #define CC_SEEK_CURRENT "current" 00305 #define CC_SEEK_TRIG "trig" 00306 00307 #define CC_STREAM "stream" // stream [stride [, mean]] 00308 00309 00310 /* 00311 * master commands - apply to master dev only 00312 */ 00313 #define MC_GET_HELP "help" 00314 #define MC_GET_NUMCHANNELS "getNumChannels" 00315 #define MC_GET_NUMSAMPLES "getNumSamples" 00316 #define MC_GET_SETSAMPLES "getSetNumSamples" 00317 #define MC_GET_STATE "getState" 00318 00319 #define MC_SET_CHANNEL_MASK "setChannelMask" // <mask> {0|1}*N 00320 #define MC_GET_CHANNEL_MASK "getChannelMask" 00321 00322 #define MC_GET_MEMORY_DEPTH "getMemoryDepth" // <channel> 00323 #define MC_SET_MODE "setMode" // <mode> <samples> [RUN_BLOCK] 00324 #define MC_GET_MODE "getMode" // <mode> <samples> 00325 #define MC_SET_ARM "setArm" 00326 #define MC_SET_ABORT "setAbort" 00327 00328 #define MC_SET_DATA_ROUTE "setDataRoute" // raw, row, channel 00329 00330 #define MC_SET_DISTRIBUTOR "setDistributor" // 0..n 00331 00332 00333 #define MC_MODE_GATED_TRANSIENT "GATED_TRANSIENT" 00334 #define MC_MODE_GATED_CONTINUOUS "GATED_CONTINUOUS" 00335 #define MC_MODE_SOFT_TRANSIENT "SOFT_TRANSIENT" 00336 #define MC_MODE_SOFT_CONTINUOUS "SOFT_CONTINUOUS" 00337 #define MC_MODE_TRIGGERED_CONTINUOUS "TRIGGERED_CONTINUOUS" 00338 00339 #define MC_SET_MODE_GC "setModeGatedContinuous" // <pre> <post> 00340 #define MC_SET_MODE_TRC "setModeTriggeredContinuous" // <pre> <post> [DIx] 00341 00342 #define DIX_DEFAULT 4 // for reference - this is the default DIx trigger line 00343 00344 00345 #define MC_STATE_STOP "ST_STOP" 00346 #define MC_STATE_ARM "ST_ARM" 00347 #define MC_STATE_RUN "ST_RUN" 00348 #define MC_STATE_TRIGGER "ST_TRIGGER" 00349 #define MC_STATE_POSTPROCESS "ST_POSTPROCESS" 00350 #define MC_STATE_CAPDONE "ST_CAPDONE" 00351 00352 #define MC_MODE_RUN_BLOCK "RUN_BLOCK" 00353 00354 #define MC_SET_ARMED "setArmed" 00355 #define MC_SET_ABORT "setAbort" 00356 00357 #define MC_GET_NUMSAMPLES "getNumSamples" 00358 00359 #define MC_SET_INTERNAL_CLOCK "setInternalClock" // <hz> [DOx] 00360 #define MC_GET_INTERNAL_CLOCK "getInternalClock" 00361 #define MC_SET_SAMPLE_TAGGING "setSampleTagging" 00362 #define MC_SET_EXTERNAL_CLOCK "setExternalClock" // <DIx> [DOx <div>] 00363 00364 #define MC_BIGDUMP "bigdump" 00365 #define MC_GET_FWREV "getFwrev" 00366 #define MC_GET_CONFIG "getConfig" 00367 #define MC_GET_CALINFO "getCalinfo" 00368 #define MC_GET_CAPTURESTATS "getCaptureStats" 00369 #define MC_GET_DEBUG "getDebug" 00370 00371 #define MC_GET_MAX_CHANNELS "getAvailableChannels" 00372 #define MC_GET_VRANGE "getVoltsRange" 00373 00374 00375 #define MC_SET_CAL "setCal" // setCal <cal-image> 00376 #define MC_WAIT_STATE "waitState" // waitState <STATE> <timeout> 00377 00378 #define MC_RESERVE_AO "reserveAO" // reserveAO <nsamples> 00379 #define MC_GET_RESERVED_AO "getReservedAO" // get reservation size 00380 00381 00382 /* 00383 * Threshold Triggering 00384 */ 00385 #define MC_TH_CLEAR_ALL "clearThresholds" 00386 #define MC_TH_SELECT "selectThresholdDistributor" // select threshold [option] 00387 #define MC_TH_SELECT1 "selectThresholdDetector" // ditto, preferred 00388 // options are 00389 #define MC_TH_BILEVEL "BILEVEL" // two levels, single board 00390 #define MC_TH_BILEVEL_MULTI "BILEVEL_MULTI" // two levels, multi board 00391 #define MC_TH_EDGE "EDGE" // edge trigger, single board 00392 #define MC_TH_EDGE_MULTI "EDGE_MULTI" // edge trigger, multi board 00393 #define MC_TH_FAST_MULTI "FAST_MULTI" // multi board sink, trigger source defined eleswhere 00394 00395 #define MC_TH_CHANNEL_SET "setChannelThreshold" // BILEVEL: <channel> <above> <below> 00396 // EDGE: <channel> <above> 0 rising 00397 // EDGE: <channel> 0 <below> falling 00398 /* 00399 * additional Master commands, Compact PCI only 00400 */ 00401 00402 #define MC_SET_SYNC_ROUTE "setSyncRoute" // <func> <dest-mask> 00403 #define MC_GET_SYNC_ROUTE "getSyncRoute" // no-args - prints all routes 00404 00405 #define MC_SET_USER_LED "setUserLed" // setUserLed <led-num> <mode> 00406 // <led-num>: { 3 or 4 } 00407 // <mode> : OFF, ON, FLASH 00408 #define MC_SET_USER_LED_ON "ON" 00409 #define MC_SET_USER_LED_OFF "OFF" 00410 #define MC_SET_USER_LED_FLASH "FLASH" 00411 00412 00413 /* 00414 * signal conditioning commands/queries 00415 * valid on SC device 00416 */ 00417 00418 #define SC_SET_DIO "setDIO" // setDIO <dio-mask> 00419 #define SC_GET_DIO "getDIO" // getDIO 00420 #define SC_SET_CHANNEL "setChannel" // setChannel <ch>,<g1>,<g2>,<v_ex> 00421 #define SC_SET_STREAMING "stream" // stream <stride> <mean> 00422 #define DIO_MASK_INPUT '-' 00423 #define DIO_MASK_OUTPUT1 '1' 00424 #define DIO_MASK_OUTPUT0 '0' 00425 #define DIO_MASK_INPUT0 'L' 00426 #define DIO_MASK_INPUT1 'H' 00427 #define DIO_CT_ACTIVE 'A' 00428 #define DIO_CT_INACTIVE 'x' 00429 00430 /* 00431 * response prefixes 00432 */ 00433 #define ACQ32_ACK "ACQ32:" 00434 #define ACQ32_ACK_FAIL "ERROR" 00435 #define SIGCOND_ACK "SIGCOND:" 00436 00437 /* 00438 * acq32 specific error codes 00439 */ 00440 00441 enum { 00442 EACQ32_NO_INCOMING_I2O = 3200, 00443 EACQ32_NO_MAPPING, 00444 EACQ32_OUT_OF_MAPPING_RANGE, 00445 EACQ32_OFFSET_NOT_ON_WHOLE_BUFFER_BOUNDARY 00446 }; 00447 00448 /* 00449 * ACQ32_IOREAD_LOCALBUF 00450 */ 00451 00452 struct READ_LOCALBUF_DESCR { 00453 short* buffer; /* MUST be buffer returned from mmap() */ 00454 int nsamples; /* max samples to return */ 00455 int istart; /* zero based start point */ 00456 int istride; /* samples to skip */ 00457 int flags; /* extra info */ 00458 }; 00459 00460 #define READ_LOCALBUF_DESCR_FLAGS_NOWAIT 0x80000000 00461 00462 #define READ_LOCALBUF_MAXCHUNK 0x200000 // MAXCHUNKSIZE 00463 00464 /* 00465 * for ACQ32_IOREAD_GETPHYSICAL, arg must be the memory mapped buffer 00466 */ 00467 /* 00468 * args for SetSyncRoute 00469 */ 00470 00471 // destinations - selection of 00472 #define MI( n ) "MI"#n // n= { 0..5 } 00473 #define MO( n ) "MO"#n // n= { 0..5 } 00474 #define J5( n ) "J5"#n // n= { 0..3 } 00475 #define J3( n ) "J3"#n // n= { 4, 5 } 00476 #define PXI_TRIG( n ) "PXI_TRIG"#n // n= { 0..7 } 00477 #define PXI_STAR "PXI_STAR" 00478 #define PXI_CLOCK10 "PXI_CLOCK10" 00479 00480 // functions - one of 00481 #define DI( n ) "DI"#n // n = { 0..5 } 00482 #define AICLK "AICLK" 00483 #define AITRIG "AITRIG" 00484 #define AOCLK "AOCLK" 00485 #define AOTRIG "AOTRIG" 00486 #define DOCLK "DOCLK" 00487 #define DOTRIG "DOTRIG" 00488 00489 00490 // used in ext clock, as well as DI 00491 #define DO( n ) "DO"#n // n = { 0..5 } 00492 /* 00493 * GUT - full flexible triggering 00494 */ 00495 00496 #define GUT_FXN_AO "AO" 00497 #define GUT_FXN_AI "AI" 00498 #define GUT_FXN_DO "DO" 00499 00500 #define GUT_PHASE( p ) "P"#p // p { 1, 2 } 00501 #define GUT_EVENT( e ) "E"#e // e { 1, 2, 3 } 00502 00503 #define GUT_SETPHASE "setPhase" // setPhase [f] <p> <n> { p = 1, 2 } 00504 #define GUT_GETPHASE "getPhase" // getPhase [f] <p> <key> { p = 1, 2 } 00505 00506 00507 #define GUT_GETPHASE_KEY_REQUESTED_SAMPLES "requested-samples" 00508 #define GUT_GETPHASE_KEY_ACTUAL_SAMPLES "actual-samples" 00509 #define GUT_GETPHASE_KEY_STATE "state" 00510 00511 #define GUT_SETEVENT "setEvent" // setEvent [f] <e> <or conditions> { e = 1, 2, 3 } 00512 #define GUT_GETEVENT "getEvent" // getEvent [f] <e> { e = 1, 2, 3 } 00513 #define GUT_FIRE_EVENT "fireEvent" // fireEvent [f] <e> { e = 1, 2, 3 } 00514 00515 #define SOFT_CLOCK "SOFT_CLOCK" 00516 #define INTERNAL_CLOCK "INTERNAL_CLOCK" 00517 00518 #define GUT_SET_CLOCK "setClock" // setClock [f] { <d>, SOFT_CLOCK INTERNAL_CLOCK } 00519 00520 #define GUT_FIRE_CLOCK "clockNow" 00521 00522 #define GUT_RESET "resetGUT" 00523 00524 00525 // event conditions 00526 00527 #define EV_TRUE "EV_TRUE" // - the event fires immediately 00528 #define EV_SOFT "EV_SOFT" //- the event is fired "fireEvent" 00529 #define EV_TRIGGER_RISING "EV_TRIGGER_RISING" // <d> - the event is a rising edge of the external trigger signal 00530 #define EV_TRIGGER_FALLING "EV_TRIGGER_FALLING" // <d> - the event is a falling edge of the external trigger signal 00531 #define EV_NONE "EV_NONE" // - clears all for this event 00532 #define EV_DATA_EXCEEDS "EV_DATA_EXCEEDS" // <channel> <value> 00533 #define EV_DATA_BELOW "EV_DATA_BELOW" // <channel> <value> 00534 00535 00536 #endif // _ACQ32IOCTL_H_ 00537
1.7.4